1. Field of the Invention
The present invention relates to a solid-state imaging device as typified by a complementary metal-oxide semiconductor (CMOS) image sensor, and a camera system.
2. Description of Related Art
In recent years, a complementary metal-oxide semiconductor (CMOS) image sensor has been paid attention as a solid-state imaging device (image sensor) to be substituted for a charge-coupled device (CCD).
This is because the CMOS image sensor overcomes various issues of CCD, including the necessity for dedicated processes for manufacturing CCD pixels and for a plurality of power supply voltages for CCD operation, and a very complicated system because a plurality of peripheral ICs are required to be combined for the operation.
A CMOS image sensor has a plurality of large merits: manufacturing processes similar to those for a general CMOS type integrated circuit can be used for manufacturing CMOS image sensors, a single power supply can drive a CMOS image sensor, and the number of peripheral ICs can be reduced because analog circuits and logic circuits manufactured by CMOS processes can be used being mixed on the same chip.
A main trend of a CCD output circuit is one channel (1-ch) output by using a floating diffusion (FD) amplifier having an FD layer.
In contrast, a main trend of a CMOS image sensor is a column parallel type in which each pixel is provided with an FD amplifier, and by selecting each row of a pixel array, and outputs of FD amplifiers are read in a column direction at the same time.
This is because it is considered that the FD amplifier disposed in each pixel is difficult to obtain a sufficient drive capability, resulting in a need for lowering the data rate, so that that parallel processing is advantageous.
Various signal output circuits have been truly proposed for a column parallel output type CMOS image sensor.
As a method used for pixel signal readout operation of the CMOS image sensor, there is a method by which signal charges to be used as an optical signal generated by a photoelectric conversion element, such as a photodiode, are sampled temporarily via a MOS switch disposed near the photoelectric conversion element in a capacitor, and the signal charges are read out.
Noises having inverse correlation to a sampling capacitor value are generally superposed upon a sampling circuit. In a pixel, when signal charges are transferred to the sampling capacitor, the signal charges are fully transferred by utilizing a potential gradient so that noises will occur at the sampling stage. However, noises are superposed when a voltage level of capacitor is reset to a reference value, which is the previous stage of the sampling.
In order to remove the noises, a correlated double sampling (CDS) is generally used. With this method, a state (reset level) immediately before sampling signal charges is read out and stored, and then a signal level after sampling is read out so that the read out signal level is subtracted from that of the stored charges, thereby eliminating the noises.
There are various specific methods of the CDS.
A general CMOS image sensor will be described below.
FIG. 1 is a diagram showing an example of a pixel of a CMOS image sensor composed of four transistors.
This pixel 10 includes, for example, a photodiode 11 as a photoelectric conversion element, and four transistors as active elements for one photodiode 11. The four transistors include a transfer transistor 12, an amplifier transistor 13, a selection transistor 14, and a reset transistor 15.
The photodiode 11 photoelectrically converts an incident light into an amount of electric charge (here, it is an electron) corresponding to the amount of the incident light.
The transfer transistor 12 is connected between the photodiode 11 and a floating diffusion FD. Upon application of a drive signal to the gate (transfer gate) of the transfer transistor via a transfer control line LTx, the transfer transistor 12 transfers the electrons photoelectrically converted by the photodiode 11 to the floating diffusion FD.
A gate of the amplifier transistor 13 is connected to the floating diffusion FD. The amplifier transistor 13 is connected to a signal line LSGN via the selection transistor 14. The amplifier transistor 13 and a constant power supply 16 located outside the pixel unit constitute a source follower.
Through the select control line LSEL, an address signal is supplied to the gate of the selection transistor 14, and when the selection transistor 14 turns on, the amplifier transistor 13 amplifies a potential of the floating diffusion to output a voltage corresponding to the potential to the output (vertical) signal line LSGN. The signal voltage outputted from each pixel is outputted to a pixel signal readout circuit via the signal line LSGN.
The reset transistor 15 is connected between a power supply line LVDD and the floating diffusion FD. When a reset signal is supplied to the gate of the reset transistor via a reset control line LRST, the reset transistor resets a potential of the floating diffusion FD to a potential of the power supply line LVDD.
More specifically, when the pixel is reset, the transfer transistor 12 is turned on to sweep-out charges accumulated in the photoelectric conversion element 11, and then the transfer transistor 12 is turned off to make the photoelectric conversion element 11 convert an optical signal into charges and accumulate the charges.
When the pixel is read out, the reset transistor 15 is turned on to reset the floating diffusion FD, and then the reset transistor 15 is turned off to output a voltage of the floating diffusion FD via the amplifier transistor 13 and the selection transistor 14. The output at this time is defined as a P-phase voltage.
Next, the transfer transistor 12 is turned on to transfer charges accumulated in the photoelectric conversion element 22 to the floating diffusion FD, and a voltage of the floating diffusion FD is outputted by the amplifier transistor 13. The output at this time is defined as a D-phase output.
By using a difference between the D-phase output and the P-phase output as an image signal, it becomes possible to remove not only variations in DC component of the output per each pixel but also a FD reset noise of the floating diffusion from the image signal.
These operations are performed for pixels of one row at a time because the respective gates of, e.g., the transfer transistor 12, the selection transistor 14, and the reset transistor 15 are connected in units of the row.
Various pixel signal readout (output) circuits of a column parallel output type CMOS image sensor have been proposed. One of the most advanced types of this circuit has an analog-digital converter unit (hereinafter abbreviated to ADC (analog digital converter)) disposed for each column to output a pixel signal as a digital signal.
A CMOS image sensor mounting the column parallel ADC of this type is disclosed, for example, in W. Yang et. al., “An integrated 800.times.600 CMOS Image System” ISSCC Digest of Technical Papers, pp. 304 and 305, February, 199) and Japanese Unexamined Patent Application Publication No. 2005-278135.
FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device (CMOS image sensor) mounting a column parallel ADC.
As shown in FIG. 2, the solid-state imaging device 20 includes a pixel unit 21 as an imaging unit, a vertical scanning circuit 22, a horizontal transfer scanning circuit 23, a timing control circuit 24, an ADC group 25, a digital-analog conversion unit (hereinafter abbreviated to DAC (digital-analog converter)) 26, an amplifier circuit (S/A) 27, and a signal processing circuit 28.
The pixel unit 21 includes photodiodes and intra-pixel amplifiers, and is constituted of pixels such as shown in FIG. 1 disposed in a matrix shape.
In the solid-state imaging device 20, the timing control circuit 24, the vertical scanning circuit 22, and the horizontal scanning circuit 23 are disposed as the control circuit for sequentially reading out a signal from the pixel unit 21. The timing control circuit generates internal clocks. The vertical scanning circuit 22 controls row addressing and row scanning. The horizontal transfer scanning circuit 23 controls column addressing and column scanning.
The ADC group 25 includes ADCs disposed at a plurality of columns, each of which includes a comparator 25-1, a counter 25-2, and a latch 25-3. The comparator 25-1 compares a reference voltage Vslop having a ramp waveform obtained by stepwise changing a reference voltage generated by DAC 26 with an analog signal obtained from a pixel at each row via a vertical signal line. The counter 25-2 counts a comparison time. The latch 25-3 holds a count result.
The ADC group 25 has an n-bit digital signal conversion function, each ADC being disposed at each vertical signal line (column line) to constitute a column parallel ADC block.
An output of each latch 25-3 is connected to a horizontal transfer line 29 having, for example, a 2n-bit width.
Amplifier circuits 27 the number of which is 2n corresponding to the horizontal transfer line 29, and a signal processing circuit 28 are disposed.
In the ADC group 25, an analog signal (potential Vs1) read out to the vertical signal line is compared with the reference voltage Vslop (a slope waveform having a gradient and changing linearly) at the comparator 25-1 disposed at each column.
In this case, the counter 25-2 disposed at each column similar to the comparator 25-1 is in operation and changes its count in one-to-one correspondence with the potential Vslop of the ramp waveform, to thereby convert a potential (analog signal) Vs1 at a vertical signal line into a digital signal.
A change in the reference voltage Vslop is used for converting a voltage change into a time change, and the converted time is counted at a period (clock) to convert the time into a digital value.
When the analog electric signal Vs1 and the reference voltage Vslop cross, the output of the comparator 25-1 is inverted to stop an input clock to the counter 25-2, and the AD conversion is then completed.
After the completion of the above-described AD conversion period, the horizontal transfer scanning circuit 23 operates to input data latched in the latches 25-3 to the signal processing circuit 28 via the horizontal transfer line 29 and the amplifier circuit 27 to generate a two-dimensional image.
In this manner, the column parallel output processing is performed.